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| Features * 0.6 m Drawn Gate Length (0.5 m Leff) Sea-of-Gates Architecture with Triple-level Metal * 5.0V, 3.3V and 2.0V Operation including Mixed Voltages * On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and * * * * * Manage Chip-to-Chip Clock Skew Compiled (Gate Level) and Embedded (Custom) SRAMs, ROM, and CAMs Available PCI, SCSI and High Speed (250 MHz) Buffers Available Easy Alternative Sourcing of Existing ASIC, FPGA and PLD Designs Design-for-Test Methods, Including JTAG, Serial and Boundary Scan and ATPG High Output Drive Capability: Up to 48 mA with Slew Rate Control ASIC ATL 60 and ATLS60 Series Description Atmel's next generation ATL60 Series CMOS ASICs are fabricated using a 0.6m drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries are available and support the major CAD software tools. As with all Atmel ASIC families, customer involvement and satisfaction is integral to all steps of the design flow. A variety of Design for Testability techniques are supported by the libraries, and a wide range of packaging options are available. The ATLS version utilizes a fine pitch staggered row on bond pads to achieve the smallest die size possible for a given pad count. The ATLS60 is only available in a limited number of PQFP packages. Table 1. ATL60 Array Organization Device Number ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60/1100 Note: Raw Gates 4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000 Routable Gates 3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000 Max Pin Count 44 68 84 100 120 144 160 184 208 226 256 304 340 380 424 480 Max I/O Pins 36 60 76 92 112 136 152 176 200 218 248 296 332 372 416 472 Gate(1) Speed 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 1. Nominal two input NAND gate with a fanout of 2 at 5.0 volts Rev. 0388D-ASIC-07/02 1 ATLS60 Array Organization Device Number ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 Note: Raw Gates 12,500 20,400 30,200 44,600 55,300 96,500 113,500 148,200 Routable Gates 8,000 13,000 17,500 26,000 32,500 57,000 67,500 88,000 Max Pin Count 80 100 120 144 160 208 225 256 Max I/O Pins 72 92 112 136 152 200 217 248 Gate(1) Speed 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 200 ps 1. Nominal two-input NAND gate with a fanout of 2 at 5.0 volts Design Design Systems Supported Atmel supports the major software systems for design with complete macro cell libraries, as well as utilities for checking the netlist and accurate pre-route delay simulations. Table 2. Design Systems Supported System Cadence(R) Design Systems, Inc. Tools OpusTM - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XLTM - Verilog Simulator BuildGatesTM - Synthesis (Ambit) ModelSim(R) - Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Generation PrimeTimeTM - Static Path VCSTM - Verilog Simulator Floorplan ManagerTM Debussy(R) First Encounter(R) Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 5.2 01.08-SP1 5.1 v2001.2.3 Mentor Graphics(R) SynopsysTM Novas Software, Inc. Silicon PerspectiveTM 2 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Design Flow Atmel provides three methods for implementing an ASIC design while maintaining the same basic design flow for each method. This flow involves both the customer and Atmel at all critical review and acceptance steps, as shown on the following page. Database Acceptance occurs when Atmel receives and accepts the complete design database. Upon completion of this critical step, Atmel performs physical place-and-route. Functional and timing simulations are performed, based on the physical design, including the generation of a back annotation report to provide the customer with the most accurate timing information available. Final Design Review is the last step of the design flow prior to generation of masks. After this acceptance step is completed, masks are generated and released, and prototype parts in ceramic packages are delivered. 3 0388D-ASIC-07/02 ASIC Design Flow Customer Kickoff Meeting (2) Atmel Customer (1) Synthesis, Translation or Conversion Atmel (1) Customer Database Submission for Underlayer Atmel Customer Underlayer Acceptance and Tapeout Atmel Customer (1) Final Database Submission Atmel (1) Customer Database Acceptance (2) Atmel Physical Design and Verification Atmel Customer Final Design Review (2) Atmel Customer Prototype Delivery (2) Notes: 1) Performed by the customer or optionally by Atmel 2) ISO 9001/QS9000 Milestone Rev.2.3-04/02 4 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Pin Definition Requirements Within the Physical Design step (i.e., layout), certain restrictions apply during pin definition. The corner pins on each die are reserved and programmable for power and ground only. All other buffer pins are fully programmable as input, output, bidirectional, clockinto-array, power, or ground. Design Options Logic Synthesis Atmel can accept Register Transfer Level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simulation as well as synthesis. VHDL or Verilog-HDL is Atmel's preferred method of performing an ASIC design. Atmel has successfully translated dozens of existing designs from most major ASIC vendors into our ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated for a pin-for-pin compatible, drop-in replacement. Atmel has successfully translated existing FPGA/PLD designs from most major vendors into our ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC. Conversion of high-volume devices (over 10,000 units) for a single or combined design is cost effective. Performance can often be optimized for speed or power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production. ASIC Design Translation FPGA and PLD Conversions 5 0388D-ASIC-07/02 ATL60 Series Cell Library Atmel's ATL60 Series ASICs make use of an extensive library of cell structures, including logic cells, buffers and inverters, multiplexers, decoders and I/O options. Soft macros are also available. The ATL60 Series PLL operates at frequencies of up to 150 MHz with minimal phase error and jitter, making it ideal for frequency synthesis of high-speed on-chip clocks and chip-to-chip synchronization. Output buffers are programmable to meet the voltage and current requirements of both PCI and SCSI. These cells are characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test arrays. Characterization is performed over the military temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product. Table 3. Cell Index Signal Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N Description One-bit full adder with buffered outputs 2-input AND 2-input AND - High-drive 3-input AND 3-input AND - High-drive 4-input AND 4-input AND - High-drive 5-input AND 2-input AND into 2-input NOR 2-input AND into 2-input NOR - High-drive Two 2-input ANDs into 2-input NOR Two 2-input ANDs into 2-input NOR - High-drive Three 2-input ANDs into 3-input NOR Three 2-input ANDs into 3-input NOR - High-drive 2-input AND into 3-input NOR 1x Buffer 2x Buffer 2x Tristate Bus Driver with Active-high Enable 2x Tristate Bus Driver with Active-low Enable 3x Buffer 4x Buffer 8x Buffer 12x Buffer 16x Buffer 7-input Carry Lookahead 2:4 Decoder 2:4 Decoder with Active-low Enable Site Count(1) 10 2 3 3 4 3 4 5 2 4 4 8 4 7 2 2 2 4 4 3 3 5 8 10 5 7 9 6 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Table 3. Cell Index (Continued) Signal Name DEC8N DFF DFFBCPX DFFBSRX DFFC DFFR DFFS DFFSR DLY1500 DLY2000 DLY6000 DSS DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR INV1 INV1D INV1Q INV1TQ INV2 INV2T INv3h INV4 INV8 INV10 JKF JKFBCPX JKFC LAT LATBG LATBH Description 3:8 Decoder with Active-low Enable D Flip-flop D Flip-flop with Asynchronous Clear and Preset with Complementary Outputs D Flip-flop with Asynchronous Set and Reset with Complementary Outputs D Flip-flop with Asynchronous Clear D Flip-flop with Asynchronous Reset D Flip-flop with Asynchronous Set D Flip-flop with Asynchronous Set and Reset Delay Buffer 1.5 ns Delay Buffer 2.1 ns Delay Buffer 6.0 ns Set Scan Flip-flop Set Scan Flip-flop with Clear and Preset Set Scan Flip-flop with Reset Set Scan Flip-flop with Set Set Scan D Flip-flop with Reset Set Scan D Flip-flop with Set Set Scan D Flip-flop with Set and Reset 1x Inverter Dual 1x Inverters Quad 1x Inverters Quad Tristate Inverter 2x Inverter 2x Tristate Inverter with Active-high Enable 3x Inverter 4x Inverter 8x Inverter 10x Inverter JK Flip-flop Clear Preset JK Flip-flop with Asynchronous Clear and Preset and Complementary Outputs JK Flip-flop with Asynchronous Clear LATCH LATCH with Complementary Outputs and Inverted Gate Signal LATCH with High-drive Complementary Outputs Site Count(1) 24 8 16 16 9 11 9 12 6 10 24 11 16 13 13 13 12 14 1 2 4 7 2 3 2 2 4 8 10 16 12 4 6 7 7 0388D-ASIC-07/02 Table 3. Cell Index (Continued) Signal Name LATR LATS LATSR LSCC LSISO MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D Description LATCH with Reset LATCH with Set LATCH with Set and Reset Voltage Level Shifter Voltage Level Shifter with Power Supply Isolation Function 2:1 MUX 2:1 MUX - High-drive 2:1 MUX with Inverted Output 2:1 MUX with Inverted Output - High-drive 2:1 MUX with Active-low Enable Quad 2:1 MUX with Active-low Enable Quad 2:1 MUX 3:1 MUX with Inverted Output 3:1 MUX with Inverted Output - High-drive 4:1 MUX 4:1 MUX with Transmission Gate Data Inputs 4:1 MUX with Transmission Gate Data Inputs - High-drive 5:1 MUX - High-drive 8:1 MUX 8:1 MUX with Active-low Enable 8:1 MUX with Transmission Gate Data Inputs - High-drive 2-input NAND Dual 2-input NAND 2-input NAND - High-drive 3-input NAND 3-input NAND - High-drive 4-input NAND 4-input NAND - High-drive 5-input NAND 5-input NAND - High-drive 6-input NAND 6-input NAND - High-drive 8-input NAND 8-input NAND - High-drive 2-input NOR Dual 2-input NOR Site Count(1) 4 6 8 4 12 4 5 3 4 4 18 14 6 8 9 10 10 14 18 20 18 2 3 2 2 3 3 4 5 6 6 7 7 7 2 3 8 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Table 3. Cell Index (Continued) Signal Name NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR8 OAI22 OIA22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Note: Description 2-input NOR - High-drive 3-input NOR 3-input NOR - High-drive 4-input NOR 4-input NOR - High-drive 5-input NOR 8-input NOR 2-input OR into 2-input NAND 2-input OR into 3-input NAND - High-drive Two 2-input ORs into 2-input NAND Two 2-input ORs into 2-input NAND - High-drive Four 2-input ORs into 4-input NAND 2-input OR into 3-input NAND 2-input OR 2-input OR - High-drive 3-input OR 3-input OR - High-drive 4-input OR 4-input OR - High-drive 5-input OR 2-input Exclusive NOR 2-input Exclusive NOR - High-drive 2-input Exclusive OR 2-input Exclusive OR - High-drive Site Count(1) 2 2 3 3 4 5 7 2 4 2 4 6 3 2 3 3 4 3 4 5 4 4 4 4 1. A single ATL60 routing site contains four transistors, two N-channel and two P-channel, aligned in columns. The number of sites used per gate varies according to the specific isolation and power requirements. Percent utilization varies from 50% to 70%, with more accurate utilization figures generated by DoubleCheckTM, the netlist checker. 9 0388D-ASIC-07/02 Table 4. CMOS Input Interface Characteristics Interface CMOS TTL Logic High 3.5V Minimum 2.0V Minimum Logic Low 1.5V Maximum 0.8V Maximum Switchpoint VDD /2 Typical 1.4V Typical Table 5. Absolute Maximum Ratings(1) Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground Maximum Operating Voltage Notes: -55C to +125C -65C to +150C -2.0V to +7.0V(2) 6.0V 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VDD + 0.75V dc, which may overshoot to +7.0V for pulses of less than 20 ns. Table 6. 5.0-volt DC Characteristics Applicable over recommended operating range from Ta = -55C to +125C, VDD = 4.5V to 5.5V (unless otherwise noted) Symbol IIH IIL IOZ IOS VIL VIL VIH VIH VT Parameter Input Leakage High Input Leakage Low (no pull-up) 40K pull-up Output Leakage (no pull-up) Output Short Circuit Current (3x buffer)(1) TTL Input Low Voltage CMOS Input Low Voltage TTL Input High Voltage CMOS Input High Voltage TTL Switching Threshold CMOS Switching Threshold Output Low Voltage Output buffer has 12 stages of drive capability with 2 mA IOL per stage Output High Voltage Output buffer has 12 stages of drive capability with -2 mA IOH per stage VDD = 5.0V, 25C VDD = 5.0V, 25C IOL = as rated VDD = 4.5V IOH = as rated VDD = 4.5V 0.7 x VDD 2.0 0.7 x VDD 1.4 2.4 0.2 0.4 Test Condition VIN = VDD, VDD = 5.5V VIN = VSS, VDD = 5.5V VIN = VSS, VDD = 5.5V VIN = VDD or VSS, VDD = 5.5V VDD = 5.5V, VOUT = VDD VDD = 5.5V, VOUT = VSS Min Typ Max 10 Units A A A mA mA -10 -100 -10 -66 66 -15 10 0.8 0.3 x VDD V V V V V V V VOL 4.2 V VOH Note: 1. This is the specification for the 3x buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. 10 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Table 7. 3.3-volt DC Characteristics Applicable over recommended operating range from Ta = -55C to +125C, VDD = 2.7V to 3.6V (unless otherwise noted) Symbol IIH IIL IOZ IOS VIL VIH VT Parameter Input Leakage High Input Leakage Low (no pull-up) Max R pull-up (U31) Output Leakage (no pull-up) Output Short Circuit Current (8 x buffer)(1) CMOS Input Low Voltage CMOS Input High Voltage CMOS Switching Threshold Output Low Voltage Output buffer has 12 stages of drive capability with 1 mA IOL per stage. Output High Voltage Output buffer has 12 stages of drive capability with -1 mA IOH per stage. VDD = 3.0V, 25C IOL = as rated VDD = 2.7V IOH = as rated VDD = 2.7V 0.7 x V DD 4.2 0.7 x V DD 1.5 0.4 Test Condition VIN = VDD, VDD = 3.6V VIN = VSS, VDD = 3.6V VIN = VSS, VDD = 3.6V VIN = VDD or VSS, V DD = 3.6 V VDD = 3.6 V, VOUT = VDD VDD = 3.6 V, VOUT = VSS Min Typ Max 5 Units A A A mA mA 0.3 x VDD V V V V -5 -25 -5 -88 88 -3 5 VOL V VOH Table 8. 2.0-volt DC Characteristics Applicable over recommended operating range from Ta = 0C to +70C, VDD = 1.8V to 2.2V (unless otherwise noted) Symbol IIH IIL IOZ IOS VIL VIH VT Parameter Input Leakage High Input Leakage Low (no pull-up) Max R pull-up (U31) Output Leakage (no pull-up) Output Short Circuit Current (8 x buffer)(1) CMOS Input Low Voltage CMOS Input High Voltage CMOS Switching Threshold Output Low Voltage Output buffer has 12 stages of drive capability with 0.5 mA IOL per stage. Output High Voltage Output buffer has 12 stages of drive capability with -0.5 mA IOH per stage. 0.8 x VDD 0.5xVDD Test Condition VIN = VDD, VDD = 2.2V VIN = VSS, VDD = 2.2V VIN = VSS, VDD = 2.2V VIN = VDD or VSS, VDD = 2.2V VDD = 2.2V, VOUT = V DD VDD = 2.2V, VOUT = V SS Min Typ Max 5 Units A A A A mA mA 0.2 x VDD V V V -5 -15 -5 -40 40 -2 5 VOL IOL as rated VDD = 1.8V 0.2 x VDD V VOH Note: IOH as rated VDD = 1.8V 0.8 x VDD V This is the specification for the 8x buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. 11 0388D-ASIC-07/02 Table 9. I/O Buffer DC Characteristics Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V Min Typ 2.4 5.6 6.6 Max Units pF pF pF Schmitt Trigger V+ V- V V+ VV TTL Positive Threshold CMOS Positive Threshold TTL Negative Threshold CMOS Negative Threshold TTL Hysteresis CMOS Hysteresis CMOS Positive Threshold CMOS Negative Threshold CMOS Hysteresis 25C, 5.0V 25C, 5.0V 25C, 5.0V 25C, 5.0V 25C, 5.0V 25C, 5.0V 25C, 3.3V 25C, 3.3V 25C, 3.3V 1.0 0.8 1.5 1.8 3.0 1.0 2.0 0.8 1.0 1.8 1.3 0.5 2.3 2.0 3.5 V V V V V V V V V I/O Buffers * Programmable output drive 2 to 24 mA IOL; -2 to -24 mA IOH at 5.0 volts 1 to 12 mA IOL; -1 to -12 mA IOH at 3.3 volts Programmable slew rate control Built-in configurable test logic * * Design for Testability Atmel supports a wide range of Design for Testability techniques to improve the percentage of a design that can be fully tested. By achieving a high degree of testability, a designer can reduce design and prototype debug time, minimize production test time, and improve board- and system-level test and diagnostic capability. Synopsys Test Compiler software is fully supported by Atmel. By using this system during design, the computer will create and add a set of scan chains to the design, and test vectors will be generated to provide greater than 95% fault coverage. This method requires only one or two added pins for Test Enable and Test Mode. This is the easiest and least expensive method of designing testability into an ASIC design. Ad hoc means of increasing testability of an ASIC are also available. Partitioning, memory array isolation, and test point insertion are encouraged and supported by the ATL60 Series ASICs. Atmel also encourages the inclusion of Built-In Self-Test (BIST) techniques whenever possible. Each of these methods is discussed in detail in the Atmel CMOS ASIC Design Manual. In addition to all of the above, the ATL60 Series ASICs also support the Joint Test Action Group (JTAG) boundary scan architecture and Test Access Port (TAP) requirements. The required soft and hard macros to implement IEEE 1149.1-compliant architecture are available in Atmel's cell library. Use of JTAG architecture requires an additional four to five pins for test mode, data, and clock signals. 12 ATL60 and ATLS60 Series 0388D-ASIC-07/02 ATL60 and ATLS60 Series Advanced Packaging The ATL60 Series ASICs are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays and ball grid arrays. High-volume on-shore and off-shore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs and are supported through Atmel's package design center. When a standard package cannot meet a customer's need, a package can be designed to precisely fit the application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations. Table 10. Package Options (Partial List) Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super BGA Low-profile Mini BGA Chip-scale BGA Flex-tape BGA FCBGA* Note: Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 168, 204, 240, 256, 304, 352, 432, 560, 600 40, 48, 49, 56, 60, 64, 80, 81, 84, 96, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 228 32, 36, 40, 48, 49, 56, 64, 81, 84, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 324 48, 49, 64, 80, 81, 84, 96, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 280 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932 * These packages require a custom design substrate. 13 0388D-ASIC-07/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R) is a registered trademark and DoubleCheck TM is a trademark of Atmel. Cadence(R) is a registered trademark and Opus TM, NC Verilog TM, PearlTM , Verilog-XL TM and BuildGatesTM are trademarks of Cadence Design Systems, Inc.; Mentor Graphics (R) and ModelSim (R) are registered trademarks and Leonardo Spectrum TM is a trademark of Mentor Graphics; Design Compiler TM, PrimeTimeTM , VCS TM and Floorplan Manager TM are trademarks and Synopsys (R) and TetraMax (R) are registered trademarks of Synopsys; Debussy (R) is a registered trademark of Novas Software, Inc.; Silicon Perspective (R) and First Encounter (R) are registered trademarks of Silicon Perspective. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0388D-ASIC-07/02 |
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